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synchronous buck controller with constant on time and valley current mode data sheet adp1878/adp1879 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features power input voltage range: 2.95 v to 20 v on-board bias regulator minimum output voltage: 0.6 v 0.6 v reference voltage with 1.0% accuracy supports all n-channel mosfet power stages available in 300 khz, 600 khz, and 1.0 mhz options no current sense resistor required power saving mode (psm) for light loads (adp1879 only) resistor programmable current limit power good with internal pull-up resistor externally programmable soft start thermal overload protection short-circuit protection standalone precision enable input integrated bootstrap diode for high-side drive starts into a precharged output available in a 14-lead lfcsp_wd package applications telecommunications and networking systems mid-to-high end servers set-top boxes dsp core power supplies typical applications circuit figure 1. general description the adp1878 / adp1879 are versatile current-mode, synchronous step-down controllers. they provide superior transient response, optimal stability, and current-limit protection by using a constant on time, pseudo fixed frequency with a programmable current-limit, current control scheme. these devices offer optimum performance at low duty cycles by using a valley, current-mode control architec- ture allowing the adp1878 / adp1879 to drive all n-channel power stages to regulate output voltages to as low as 0.6 v. the adp1879 is the power saving mode (psm) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the adp1879 power saving mode (psm) section for more information). available in three frequency options (300 khz, 600 khz, and 1.0 mhz) plus the psm option, the adp1878 / adp1879 are well suited for a wide range of applications that require a single input power supply range from 2.95 v to 20 v. low voltage biasing is supplied via a 5 v internal low dropout regulator (ldo). in addition, soft start programmability is included to limit input inrush current from the input supply during startup and to provide reverse current protection during precharged output conditions. the low-side current sense, current gain scheme and integration of a boost diode, together with the psm/forced pulse-width modulation (pwm) option, reduce the external device count and improve efficiency. the adp1878 / adp1879 operate over the ?40c to +125c junction temperature range and are available in a 14-lead lfcsp_wd package. figure 2. adp1878/ adp1879 efficiency vs. load current (v out = 1.8 v, 300 khz) comp bst fb drvh gnd sw vreg res drvl ss c ss pgnd vin c c c vreg c vreg2 c c2 r c r bot r top v out en 10k ? v reg q1 q2 l c out v out c bst load c in v in = 2.95v to 20 v adp1878/ adp1879 r res pgood r pgd v ext 09441-001 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m ? infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-102
adp1878/adp1879 data sheet rev. a | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ....................................................... 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 17 block diagram ............................................................................ 17 startup .......................................................................................... 18 soft start ...................................................................................... 18 precision enable circuitry ........................................................ 18 undervoltage lockout ............................................................... 18 on-board low dropout (ldo) regulator ............................. 18 thermal shutdown ..................................................................... 19 programming resistor (res) detect circuit .......................... 19 valley current-limit setting .................................................... 19 hiccup mode during short circuit ......................................... 21 synchronous rectifier ................................................................ 21 adp1879 power saving mode (psm) ...................................... 21 timer operation ......................................................................... 22 pseudo fixed frequency............................................................ 22 power-good monitoring ........................................................... 23 applications information .............................................................. 24 feedback resistor divider ........................................................ 24 inductor selection ...................................................................... 24 output ripple voltage (v rr ) .................................................. 24 output capacitor selection ....................................................... 24 compensation network ............................................................ 25 efficiency consideration ........................................................... 26 input capacitor selection .......................................................... 27 thermal considerations ............................................................ 27 design example .......................................................................... 29 external component recommendations .................................... 31 layout considerations ................................................................... 33 ic section (left side of evaluation board) ............................. 35 power section ............................................................................. 35 differential sensing .................................................................... 36 typical application circuits ......................................................... 37 12 a, 300 khz high current application circuit .................. 37 5.5 v input, 600 khz current application circuit ................ 37 300 khz high current application circuit ............................ 38 packaging and ordering information ......................................... 39 outline dimensions ................................................................... 39 ordering guide .......................................................................... 40 revision history 6/12rev. 0 to rev. a changes to table 1 ............................................................................. 3 7/11revision 0: initial version
data sheet adp1878/adp1879 rev. a | page 3 of 40 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). vreg = 5 v, bst ? sw = vreg ? v rect_drop (see figure 40 to figure 42). vin = 12 v. the specifications are valid for t j = ?40c to +125c, unless otherwise specified. table 1. parameter symbol test conditions/comments min typ max unit power supply characteristics high input voltage range vin c vin = 22 f(25 v rating) right at pin 1 to pgnd (pin 11) adp1878acpz-0.3-r7/adp1879acpz-0.3-r7 (300 khz) 2.95 12 20 v adp1878acpz-0.6-r7/adp1879acpz-0.6-r7 (600 khz) 2.95 12 20 v adp1878acpz-1.0-r7/adp1879acpz-1.0-r7 (1.0 mhz) 3.25 12 20 v quiescent current i q_reg + i q_bst fb = 1.5 v, no switching 1.1 ma shutdown current i reg,sd + i bst,sd en < 600 mv 140 225 a undervoltage lockout uvlo rising vin (see figure 35 for temperature variation) 2.65 v uvlo hysteresis falling vin from operational state 178 mv internal regulator characteristics do not load vreg externally because it is intended to bias internal circuitry only vreg operational output voltage vreg c vreg = 4.7 f to pgnd, 0.22 f to gnd, v in = 2.95 v to 20 v adp1878acpz-0.3-r7/adp1879acpz-0.3-r7 (300 khz) 2.75 5 5.5 v adp1878acpz-0.6-r7/adp1879acpz-0.6-r7 (600 khz) 2.75 5 5.5 v adp1878acpz-1.0-r7/adp1879acpz-1.0-r7 (1.0 mhz) 3.05 5 5.5 v vreg output in regulation v in = 7 v, 100 ma 4.82 4.981 5.16 v v in = 12 v, 100 ma 4.83 4.982 5.16 v load regulation 0 ma to 100 ma, v in = 7 v 32 mv 0 ma to 100 ma, v in = 20 v 34 mv line regulation v in = 7 v to 20 v, 20 ma 1.8 mv v in = 7 v to 20 v, 100 ma 2.0 mv vin to vreg dropout voltage 100 ma out of vreg, v in 5 v 306 415 mv short vreg to pgnd v in = 20 v 229 320 ma soft start connect external capacitor from ss pin to gnd, soft start period calculation c ss = 10 nf/ms 10 nf/ms error amplifer fb regulation voltage v fb t j = 25c 600 mv t j = ?40c to +85c 596 600 604 mv t j = ?40c to +125c 594.2 600 605.8 mv transconductance g m 320 496 670 s fb input leakage current i fb, leak fb = 0.6 v, en = vreg 1 50 na current sense amplifier gain programming resistor (res) value from res to pgnd res = 47 k 1% 2.7 3 3.3 v/v res = 22 k 1% 5.5 6 6.5 v/v res = none 11 12 13 v/v res = 100 k 1% 22 24 26 v/v switching frequency typical values measured at 50% time points with 0 nf at drvh and drvl; maximum values are guaranteed by bench evaluation 1 adp1878acpz-0.3-r7/ adp1879acpz-0.3-r7 300 khz on time v in = 5 v, v out = 2 v, t j = 25c 1120 1200 1345 ns minimum on time v in = 20 v 145 190 ns minimum off time 84% duty cycle (maximum) 340 400 ns
adp1878/adp1879 data sheet rev. a | page 4 of 40 parameter symbol test conditions/comments min typ max unit adp1878acpz-0.6-r7/ adp1879acpz-0.6-r7 600 khz on time v in = 5 v, v out = 2 v, t j = 25c 500 540 605 ns minimum on time v in = 20 v, v out = 0.8 v 82 110 ns minimum off time 65% duty cycle (maximum) 340 400 ns adp1878acpz-1.0-r7/ adp1879acpz-1.0-r7 1.0 mhz on time v in = 5 v, v out = 2 v, t j = 25c 285 312 360 ns minimum on time v in = 20 v 52 85 ns minimum off time 45% duty cycle (maximum) 340 400 ns output driver characteristics high-side driver output source resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 2.20 3 output sink resistance i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.72 1 rise time 2 t r, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 59) 25 ns fall time 2 t f, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 60) 11 ns low-side driver output source resistance i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 1.5 2.2 output sink resistance i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.7 1 rise time 2 t r,drvl v reg = 5.0 v, c in = 4.3 nf (see figure 60) 18 ns fall time 2 t f,drvl v reg = 5.0 v, c in = 4.3 nf (see figure 59) 16 ns propagation delays drvl fall to drvh rise 2 t tpdhdrvh bst ? sw = 4.4 v (see figure 59) 15.7 ns drvh fall to drvl rise 2 t tpdhdrvl bst ? sw = 4.4 v (see figure 60) 16 ns sw leakage current i swleak bst = 25 v, sw = 20 v, v reg = 5 v 110 a integrated rectifier channel impedance i sink = 10 ma 22.3 precision enable threshold logic high level v in = 2.9 v to 20 v, v reg = 2.75 v to 5.5 v 605 634 663 mv enable hysteresis v in = 2.9 v to 20 v, v reg = 2.75 v to 5.5 v 31 mv comp voltage comp clamp low voltage v comp(low) tie en pin to vreg to enable device (2.75 v v reg 5.5 v) 0.47 v comp clamp high voltage v comp(high) (2.75 v v reg 5.5 v) 2.55 v comp zero current threshold v comp_zct (2.75 v v reg 5.5 v) 1.10 v thermal shutdown t tmsd thermal shutdown threshold rising temperature 155 c thermal shutdown hysteresis 15 c current limit hiccup current-limit timing comp = 2.4 v 6 ms overvoltage and power- good thresholds pgood fb power-good threshold fb pgd v fb rising during system power up 542 566 mv fb power-good hysteresis 34 55 mv fb overvoltage threshold fb ov v fb rising during overvoltage event, i pgood = 1 ma 691 710 mv fb overvoltage hysteresis 35 55 mv pgood low voltage during sink v pgood i pgood = 1 ma 143 200 mv pgood leakage current pgood = 5 v 1 100 na 1 the maximum specified values are with the closed loop measured at 10% to 90% time points (see figure 59 and figure 60), c gate = 4.3 nf, and the high- and low-side mosfets being infin eon bsc042n03ms g. 2 not automatic test equipment (ate) tested.
data sheet adp1878/adp1879 rev. a | page 5 of 40 absolute maximum ratings table 2. parameter rating vreg to pgnd, gnd ?0.3 v to +6 v vin, en, pgood to pgnd ?0.3 v to +28 v fb, comp, res, ss to gnd ?0.3 v to (vreg + 0.3 v) drvl to pgnd ?0.3 v to (vreg + 0.3 v) sw to pgnd ?2.0 v to +28 v bst to sw ?0.6 v to (vreg + 0.3 v) bst to pgnd ?0.3 v to +28 v drvh to sw ?0.3 v to vreg pgnd to gnd 0.3 v pgood input current 35 ma ja (14-lead lfcsp_wd) 4-layer board 30c/w operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 maximum soldering lead temperature (10 sec) 300c absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to pgnd. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. boundary condition in determining the values given in table 2 and table 3, natural convection is used to transfer heat to a 4-layer evaluation board. table 3. thermal resistance package type ja unit ja (14-lead lfcsp_wd) 4-layer board 30 c/w esd caution stresses abo v e those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de v ice reliability.
adp1878/adp1879 data sheet rev. a | page 6 of 40 pin configuration and fu nction descriptions figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vin high-side input voltage. connect vin to the drain of the high-side mosfet. 2 comp output of the error amplifier. connect compensation network between this pin and agnd to achieve stability (see the compensation network section). 3 en ic enable. connect en to vreg to enable the ic. wh en pulled down to agnd externally, en disables the ic. 4 fb noninverting input of the internal error amplifier. th is is the node where the feedback resistor is connected. 5 gnd analog ground reference pin of the ic. connect all sensitive analog components to this ground plane (see the layout considerations section). 6 res current sense gain resistor (external). connect a resistor between the res pin and gnd (pin 5). 7 vreg internal regulator supply bias voltage for the adp1878 / adp1879 controller (includes the output gate drivers). connecting a bypass capacitor of 1 f directly from this pin to pgnd and a 0.1 f capacitor across vreg and gnd are recommended. 8 ss soft start input. connect an external capacitor to gnd to program the soft start period. there is a capacitance value of 10 nf for every 1 ms of soft start delay. 9 pgood open-drain power-good output. pgood sinks current when fb is out of regulation or during thermal shutdown. connect a 3 k resistor between pgood and vreg. leave pgood unconnected if it is not used. 10 drvl drive output for the external low-side, n-channel mosfet. th is pin also serves as the current sense gain setting pin (see figure 69). 11 pgnd power ground. ground for the low-side gate driver and low-side n-channel mosfet. 12 drvh drive output for the external high-side n-channel mosfet. 13 sw switch node connection. 14 bst bootstrap for the high-side n-channel mosfet gate drive ci rcuitry. an internal boot rectifier (diode) is connected between vreg and bst. a capacitor from bst to sw is requ ired. an external schottky diode can also be connected between vreg and bst for increased gate drive capability. ep exposed pad. connect the exposed pa d to the analog ground pin (gnd). top view (not to scale) 09441-003 14 13 12 11 10 9 8 6 5 4 2 3 1 7 vin comp en fb gnd res vreg bst sw drvh pgnd drvl pgood ss adp1878 / a dp1879 notes 1. connect the exposed pad to the analog ground pin (gnd).
data sheet adp1878/adp1879 rev. a | page 7 of 40 typical performance characteristics figure 4. efficiency300 khz, v out = 0.8 v figure 5. efficiency300 khz, v out = 1.8 v figure 6. efficiency300 khz, v out = 7 v figure 7. efficiency600 khz, v out = 0.8 v figure 8. efficiency600 khz, v out = 1.8 v figure 9. efficiency600 khz, v out = 5 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 300khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-004 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m ? infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-005 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 7v f sw = 300khz wrth inductor: 7443551200, l = 2.0h, dcr = 2.6m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-006 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 600khz wrth inductor: 744355147, l = 0.47h, dcr = 0.67m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-007 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 600khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-008 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 600khz wrth inductor: 744318180, l = 1.4h, dcr = 3.2m ? infineon fets: bsc042n03ms g (upper/lower) v in = 20v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 20v v in = 16.5v 09441-009
adp1878/adp1879 data sheet rev. a | page 8 of 40 figure 10. efficiency1.0 mhz, v out = 0.8 v figure 11. efficiency1.0 mhz, v out = 1.8 v figure 12. efficiency1.0 mhz, v out = 5 v figure 13. output voltage accuracy300 khz, v out = 0.8 v figure 14. output voltage accuracy300 khz, v out = 1.8 v figure 15. output voltage accuracy300 khz, v out = 7 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 1.0mhz wrth inductor: 744303012, l = 0.12h, dcr = 0.33m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-010 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 1.0mhz wrth inductor: 744303022, l = 0.22h, dcr = 0.33m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-011 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 1.0mhz wrth inductor: 744355090, l = 0.9h, dcr = 1.6m ? infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09441-012 0.807 0.806 0.805 0.804 0.803 0.802 0.801 0.800 0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09441-013 1.821 1.816 1.811 1.806 1.801 1.796 1.791 1.786 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09441-014 7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 09441-015
data 4 heet adp1878/adp1879 rev. a | page 9 of 40 figure 16 . output voltage accuracy 600 khz, v out = 0.8 v figure 17 . output voltage accuracy 600 khz, v out = 1.8 v figure 18 . output voltage accuracy 600 khz, v out = 5 v figure 19 . output voltage accuracy 1.0 mhz, v out = 0.8 v figure 20 . output voltage accuracy 1.0 mhz, v out = 1.8 v figure 21 . output voltage accuracy 1.0 mhz, v out = 5 v 0.808 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0 1000 2000 3000 4000 5000 6000 7000 8000 10,000 9000 frequency (khz) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 09441-016 1.818 1.770 1.772 1.774 1.776 1.778 1.780 1.782 1.784 1.786 1.788 1.790 1.792 1.794 1.796 1.798 1.800 1.802 1.804 1.806 1.808 1.810 1.812 1.814 1.816 0 12,000 10,500 9000 7500 6000 4500 3000 1500 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09441-017 5.030 5.025 5.005 5.010 5.015 5.020 5.000 4.995 4.990 4.985 4.980 4.975 4.970 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v v in = 20v 09441-018 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 0.787 0.789 0.791 0.793 0.795 0.797 0.799 0.801 0.803 0.805 0.807 09441-019 1.820 1.815 1.810 1.805 1.800 1.795 1.790 0 10,000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09441-020 7200 6400 5600 4800 4000 2400 1600 3200 0 9600 8800 8000 800 5.04 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09441-021
adp1878/adp1879 data 4 heet rev. a | page 10 of 40 figure 22 . feedback voltage vs. temperature figure 23 . switching frequency vs. high input voltage, 300 khz, 10% of 12 v figure 24 . switching frequency vs. high input voltage, 600 khz, v out = 1.8 v, v in range = 13 v to 16.5 v figure 25 . switching frequency vs. high input voltage, 1.0 mhz, v in range = 13 v to 16.5 v figure 26 . frequency vs. load current, 300 khz, v out = 0.8 v figure 27 . frequency vs. load current, 300 khz, v out = 1.8 v 601.0 600.5 600.0 599.5 599.0 598.5 598.0 597.5 597.0 ?40.0 ?7.5 25.0 57.5 90.0 122.5 feedback voltage (v) temperature (c) v reg = 5v, v in = 13v v reg = 5v, v in = 20v 09441-022 325 315 305 295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 switching frequency (khz) v in (v) +125c +25c ?40c no load 09441-023 650 600 550 500 450 400 13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2 switching frequency (khz) v in (v) +125c +25c ?40c no load 09441-024 900 880 860 840 820 800 780 760 740 720 700 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 switching frequency (khz) v in (v) +125c +25c ?40c 09441-025 280 190 205 220 235 250 265 0 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 13v v in = 20v v in = 16.5v +125c +25c ?40c 09441-026 330 240 250 260 270 280 290 300 310 320 0 15,000 12,000 13,500 10,500 9000 7500 6000 4500 3000 1500 frequency (khz) load current (ma) v in = 20v v in = 13v v in = 16.5v +125c +25c ?40c 09441-027
data 4 heet adp1878/adp1879 rev. a | page 11 of 40 figure 28 . frequency vs. load current, 300 khz , v out = 7 v figure 29 . frequency vs. load current, 600 khz, v out = 0.8 v figure 30 . frequency vs. load current, 600 khz, v out = 1.8 v figure 31 . frequency vs. load current, 600 khz, v out = 5 v figure 32 . frequency vs. load current, v out = 1.0 mhz, 0.8 v figure 33 . frequency vs. load current, 1.0 mhz, v out = 1.8 v 338 298 302 306 310 314 318 322 326 330 334 0 6400 7200 8000 8800 560048004000320024001600800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 09441-028 300 330 360 390 420 450 480 510 540 0 12,000 1200 2400 3600 4800 6000 7200 8400 9600 10,800 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09441-029 675 495 515 535 555 575 595 615 635 655 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09441-030 740 621 628 635 642 649 656 663 670 677 684 691 698 705 712 719 726 733 0 9600 8800 8000 7200 6400 5600 4800 4000 3200 2400 1600800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 09441-031 850 775 700 625 550 475 400 0 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09441-032 550 625 700 775 850 925 1000 1075 1150 1225 0 12,000 9600 10,800 8400 7200 6000 4800 3600 2400 1200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09441-033
adp1878/adp1879 data 4 heet rev. a | page 12 of 40 figure 34 . frequency vs. load current, 1.0 mhz, v out = 5 v figure 35 . uvlo vs. temperature figure 36 . maximum duty cycle vs. frequency figure 37 . maximum duty cycle vs. high voltage input (v in ) figure 38 . minimum off time vs. temperature figure 39 . minimum off time vs. v reg (low input voltage) 1000 1450 1400 1350 1300 1250 1200 1150 1100 1050 0 8000 800 1600 2400 3200 4000 4800 5600 6400 7200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09441-034 2.649 2.658 2.657 2.656 2.655 2.654 2.653 2.652 2.651 2.650 ?40 120 10080604020 0 ?20 uvlo (v) temperature (c) 09441-035 55 60 65 70 75 80 85 90 95 300 400 500 600 700 800 900 1000 maximum duty cycle (%) frequency (khz) +125c +25c ?40c 09441-036 62 64 66 68 70 72 74 76 78 80 82 5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 maximum duty cycle (%) v in (v) +125c +25c ?40c 09441-037 180 680 630 580 530 480 430 380 330 280 230 ?40 120 10080604020 0 ?20 minimum off time (ns) temperature (c) v reg = 2.7v v reg = 5.5v v reg = 3.6v 09441-038 180 680 630 580 530 480 430 380 330 280 230 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 minimum off time (ns) v reg (v) +125 c +25 c ?40 c 09441-039
data 4 heet adp1878/adp1879 rev. a | page 13 of 40 figure 40 . internal rectifier drop vs. frequency figure 41 . internal boost rectifier drop vs. vreg (low input voltage) over v in variation figure 42 . internal boost rectifier drop vs. v reg figure 43 . low - side mosfet body diode conduction time vs. v reg figure 44 . power saving mode (psm) operational waveform, 100 ma figure 45 . psm waveform at light load, 500 ma 80 800 720 640 560 480 400 320 240 160 300 400 500 600 700 800 900 1000 rectifier drop (mv) frequency (khz) v reg = 2.7v v reg = 5.5v v reg = 3.6v +125c +25c ?40c 09441-040 80 1280 720 640 560 480 1040 1120 1200 960 880 800 400 320 240 160 2. 7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rectifier drop (mv) v reg (v) v in = 5.5v v in = 16.5v v in = 13v 1mhz 300khz t a = 25c 09441-041 80 720 640 560 480 400 320 240 160 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rectifier drop (mv) v reg (v) 1mhz 300khz +125c +25c ?40c 09441-042 8 80 64 72 56 48 40 32 24 16 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 body diode conduction time (ns) v reg (v) 1mhz 300khz +125c +25c ?40c 09441-043 ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m400ns a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09441-044 ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m4.0s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09441-045
adp1878/adp1879 data sheet rev. a | page 14 of 40 figure 46. ccm operation at heavy load, 12 a (see figure 95 for application circuit) figure 47. load transient steppsm enabled, 12 a (see figure 95 application circuit) figure 48. positive step during heavy load transient behaviorpsm enabled, 12 a, v out = 1.8 v (see figure 95 application circuit) figure 49. negative step during heavy load transient behaviorpsm enabled, 12 a (see figure 95 application circuit) figure 50. load transient stepforced pwm at light load, 12 a (see figure 95 application circuit) figure 51. positive step during heavy load transient behaviorforced pwm at light load, 12 a, v out = 1.8 v (see figure 95 application circuit) ch1 5a ? ch3 10v ch4 100mv b w m400ns a ch3 2.20v t 30.6% 1 3 4 output voltage inductor current sw node 09441-046 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m2ms a ch1 3.40a t 75.6% 1 2 3 4 output voltage 12a step sw node low side 0 9441-047 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 30.6% 1 2 3 4 output voltage 12a positive step sw node low side 09441-048 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 48.2% 1 2 3 4 output voltage 12a negative step sw node low side 09441-049 ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m2ms a ch1 6.20a t 15.6% 1 2 3 4 output voltage 12a step sw node low side 09441-050 ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m20s a ch1 6.20a t 43.8% 1 2 3 4 output voltage 12a positive step sw node low side 09441-051
data sheet adp1878/adp1879 rev. a | page 15 of 40 figure 52. negative step during heavy load transient behaviorforced pwm at light load, 12 a (see figure 95 application circuit) figure 53. output short-circuit behavior leading to hiccup mode figure 54. magnified waveform during hiccup mode figure 55. start-up behavior at heavy load, 12 a, 300 khz (see figure 95 application circuit) figure 56. power-down waveform during heavy load figure 57. output voltage ripple waveform during psm operation at light load, 2 a ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m10s a ch1 5.60a t 23.8% 1 2 3 4 output voltage 12a negative step sw node low side 09441-052 ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 920mv t 49.4% 1 2 3 4 output voltage inductor current sw node low side 09441-053 ch1 5v b w ch2 10a ? ch3 10v ch4 5v m10s a ch2 8.20a t 36.2% 1 2 3 4 output voltage inductor current sw node low side 09441-054 ch1 2v b w ch2 5a ? ch3 10v ch4 5v m2ms a ch1 720mv t 32.8% 1 2 3 4 output voltage inductor current sw node low side 09441-055 ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 720mv t 41.6% 1 2 3 4 output voltage inductor current sw node low side 09441-056 ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m2s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09441-057
adp1878/adp1879 data sheet rev. a | page 16 of 40 figure 58. output driver s and sw node waveforms figure 59. high-side driver rising and low-side falling edge waveforms (c in = 4.3 nf (high-/low-side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) figure 60. high-side driver falling and low-side rising edge waveforms (c in = 4.3 nf (high-/low-side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3)) figure 61. transconductance vs. temperature figure 62. transconductance vs. v reg figure 63. quiescent current vs. v reg 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side t a = 25c 09441-058 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side 16ns ( t f ,drvl ) 25ns ( t r ,drvh ) 22ns ( t pdh drvh ) t a = 25c 09441-059 2 ch2 5v ch3 5v math 2v 20ns ch4 2v m20ns a ch2 4.20v t 39.2% 3 m 4 high side hs minus sw sw node low side 18ns ( t r ,drvl ) 24ns ( t pdh ,drvl ) 11ns ( t f ,drvh ) t a = 25c 09441-060 570 550 530 510 490 470 450 430 ?40 ?20 120 10080604020 0 transconductance (s) temperature (c) v reg = 5.5v v reg = 3.6v v reg = 2.7v 09441-061 680 330 380 430 480 530 580 630 2.7 3.0 5.4 4.8 5.1 4.54.23.93.63.3 transconductance (s) v reg (v) +125c +25c ?40c 09441-062 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 2.7 5.5 5.1 4.7 4.3 ?40c +25c +125c 3.9 3.5 3.1 quiescent current (ma) v reg (v) 09441-063
data sheet adp1878/adp1879 rev. a | page 17 of 40 theory of operation block diagram figure 64. adp1878 / adp1879 block diagram the adp1878 / adp1879 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on time, pseudo fixed frequency with a programmable current sense gain, current control scheme. in addition, these devices offer optimum performance at low duty cycles by using a valley, current- mode control architecture. this allows the adp1878 / adp1879 to drive all n-channel power stages to regulate output voltages to as low as 0.6 v. 09441-064 drvh gnd irev comp adp1878/adp1879 c r (trimmed) vreg t on timer t on = 2rc(v out /v in ) i sw information sw filter state machine ton bg_ref in_psm in_ss pwm comp hs_0 hs sw ls ls_0 irev level shift hs vreg ls vreg 300k ? 800k ? 8k? sw drvl pgnd bst vin psm ref_zero in_hiccup ss comp error amp ss_ref 0.6v lower comp clamp ref_zero cs amp pwm fb comp vreg i ss ss 0.4v adc res detect and gain set cs gain set bias block and reference ref ldo precision enable 630mv to enable all blocks en res 530mv 690mv fb 600mv pgoo d threshold/ hysteresis
adp1878/adp1879 data sheet rev. a | page 18 of 40 startup each adp1878 / adp1879 has an internal regulator (vreg) for biasing and supplying power for the integrated n-channel mosfet drivers. place a bypass capacitor directly across the vreg (pin 7) and pgnd (pin 13) pins. included in the power- up sequence is the biasing of the current sense amplifier, the current sense gain circuit (see the programming resistor (res) detect circuit section), the soft start circuit, and the error amplifier. the current sense blocks provide valley current information (see the programming resistor (res) detect circuit section) and they are a variable of the compensation equation for loop stability (see the compensation network section). in a process performed by the res detect circuit, the valley current informa- tion is extracted by forcing 0.4 v across the res and pgnd pins generating current. the current through the res resistor is used to set the current sense amplifier gain (see the programming resistor (res) detect circuit section). this process takes approx- imately 800 s, after which time the drive signal pulses appear at the drvl and drvh pins synchronously, and the output voltage begins to rise in a controlled manner through the soft start sequence. the soft start and error amplifier blocks determine the rise time of the output voltage (see the soft start section). at the beginning of a soft start, the error amplifier charges the external compensa- tion capacitor, causing the comp pin to rise (see figure 65). tying the vreg pin to the en pin via a pull-up resistor causes the voltage at the en pin to rise above the enable threshold of 630 mv, thereby enabling the adp1878 / adp1879 . figure 65. comp voltage range soft start the adp1878 employs externally programmable, soft start circuitry that charges up a capacitor tied to the ss pin to gnd. this prevents input inrush current through the external mosfet from the input supply (v in ). the output tracks the ramping voltage by producing pwm output pulses to the high-side mosfet. the purpose is to limit the inrush current from the high voltage input supply (v in ) to the output (v out ). precision enable circuitry the adp1878 / adp1879 have precision enable circuitry. the precision enable threshold is 630 mv including 30 mv of hysteresis (see figure 66). connecting the en pin to gnd disables the adp1878 / adp1879 , reducing the supply current of the device to approximately 140 a. figure 66. connecting en pin to vreg via a pull-up resistor to enable the adp1878 / adp1879 undervoltage lockout the undervoltage lockout (uvlo) feature prevents the device from operating both the high- and low-side n-channel mosfets at extremely low or undefined input voltage (v in ) ranges. operation at an undefined bias voltage can result in the incorrect propagation of signals to the high-side power switches. this, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. the uvlo level is set at 2.65 v (nominal). on-board low dropout (ldo) regulator the adp1878 / adp1879 use an on-board ldo to bias the internal digital and analog circuitry. with proper bypass capacitors connected to the vreg pin (output of the internal ldo), this pin also provides power for the internal mosfet drivers. it is recommended to float vreg if vin is used for greater than 5.5 v operation. the minimum voltage at which bias is guaranteed to operate is 2.75 v at vreg (see figure 67). figure 67. on-b oard regulator for applications where vin is decoupled from vreg, the minimum voltage at vin must be 2.9 v. it is recommended to tie vin and vreg together if the vin pi n is subjected to a 2.75 v rail. comp >2.4v 2.4v 1.0v 500mv 0v hiccup mode initialized maximum current (upper clamp) zero current usable range only after soft start period if continuous conduction mode of operation is selected. lower clamp 09441-066 precision enable comp. to enable all blocks en 630mv v reg 10k ? 09441-065 ref v reg vin on-board regulator 09441-067
data sheet adp1878/adp1879 rev. a | page 19 of 40 table 5. power input and ldo output configurations vin vreg comments >5.5 v float must use the ldo <5.5 v connect to vin ldo drop voltage is not realized (that is, if vin = 2.75 v, then vreg = 2.75 v) <5.5 v float ldo drop is realized vin ranging above and below 5.5 v float ldo drop is realized, minimum vin recommendation is 2.95 v thermal shutdown thermal shutdown is a protection feature that prevents the ic from damage caused by a very high operating junction temper- ature. if the junction temperature of the device exceeds 155c, the device enters the thermal shutdown state. in this state, the device shuts off both the high- and low-side mosfets and disables the entire controller immediately, thus reducing the power con- sumption of the ic. the device resumes operation after the junction temperature of the device cools to less than 140c. programming resistor (res) detect circuit upon startup, one of the first blocks to become active is the res detect circuit. this block powers up before soft start begins. it forces a 0.4 v reference value at the res pin (see figure 68) and is programmed to identify four possible resistor values: 47 k, 22 k, open, and 100 k. the res detect circuit digitizes the value of the resistor at the res pin (pin 6). an internal adc outputs a 2-bit digital code that is used to program four separate gain configurations in the current sense amplifier (see figure 69). each configuration corre- sponds to a current sense gain (a cs ) of 3 v/v, 6 v/v, 12 v/v, or 24 v/v, respectively (see table 6 and table 7). this variable is used for the valley current-limit setting, which sets up the appropriate current sense gain for a given application and sets the compensation necessary to achieve loop stability (see the valley current-limit setting section and the compensation network section). figure 68. programming resistor location figure 69. res detect circuit for current sense gain programming table 6. current sense gain programming resistor a cs 47 k 3 v/v 22 k 6 v/v open 12 v/v 100 k 24 v/v valley current-limit setting the architecture of the adp1878 / adp1879 is based on valley current-mode control. the current limit is determined by three components: the r on of the low-side mosfet, the output voltage swing of the current sense amplifier, and the current sense gain. the output range of the current sense amplifier is internally fixed at 1.4 v. the current sense gain is programmable via an external resistor at the res pin (see the programming resistor (res) detect circuit section). the r on of the low-side mosfet can vary over temperature and usually has a positive t c (meaning that it increases with temperature); therefore, it is recommended to program the current sense, gain resistor based on the rated r on of the mosfet at 125c. because the adp1878 / adp1879 are based on valley current control, the relationship between i clim and i load is 1 2 where: k i is the ratio between the inductor ripple current and the desired average load current (see figure 70). i clim is the desired valley current limit. i load is the current load. establishing k i helps to determine the inductor value (see the inductor selection section), but in most cases, k i = 0.33. figure 70. valley current limit to average current relation drvh drvl q1 sw q2 res cs gain programming 09441-068 sw pgnd cs gain set cs amp adc res 0.4v 09441-069 load current valley current limit ripple current = i load 3 09441-070
adp1878/adp1879 data sheet rev. a | page 20 of 40 when the desired valley current limit (i clim ) has been determined, the current sense gain can be calculated as follows: 1.4 v where: r on is the channel impedance of the low-side mosfet. a cs is the current sense gain multiplier (see table 6 and table 7). although the adp1878 / adp1879 have only four discrete current sense gain settings for a given r on variable, table 7 and figure 71 outline several available options for the valley current setpoint based on various r on values. table 7. valley current limit program (see figure 71) r on (m) valley current level (a) 1 47 k, 22 k, open, 100 k, a cs = 3 v/v a cs = 6 v/v a cs = 12 v/v a cs = 24 v/v 1.5 38.9 2 29.2 2.5 23.3 3 39.0 19.5 3.5 33.4 16.7 4.5 26.0 13 5 23.4 11.7 5.5 21.25 10.6 10 23.3 11.7 5.83 15 31.0 15.5 7.75 7.5 18 26.0 13.0 6.5 3.25 1 blank cells are not applicable. figure 71. valley current-limit value vs. r on of the low-side mosfet for each programming resistor (res) the valley current limit is programmed as listed in table 7 and shown in figure 71. the inductor that is chosen must be rated to handle the peak current, which is equal to the valley current from table 7 plus the peak-to-peak inductor ripple current (see the inductor selection section). in addition, the peak current value must be used to compute the worst-case power dissipation in the mosfets (see figure 72). figure 72. valley current-limit threshold in relation to inductor ripple current 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 valley current limit (a) r on (m ? ) 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 res = 47k ? a cs = 3v/v res = 22k ? a cs = 6v/v res = no res a cs = 12v/v res = 100k ? a cs = 24v/v 09441-071 inductor current valley current-limit threshold (set for 25a) ? i = 33% of 30a cs amp output swing current sense amplifier output 2.4v 1v 0a 35a 30a 32.25a 37a 49 a 39.5a ? i = 45% of 32.25a ? i = 65% of 37a maximum dc load current 09441-072
data sheet adp1878/adp1879 rev. a | page 21 of 40 figure 73. idle mode entry sequence due to current-limit violation hiccup mode during short circuit a current-limit violation occurs when the current across the source and drain of the low-side mosfet exceeds the current- limit setpoint. when 32 current-limit violations are detected, the controller enters idle mode and turns off the mosfets for 6 ms, allowing the converter to cool down. then, the controller reestablishes soft start and begins to cause the output to ramp up again (see figure 73). while the output ramps up, the current sense amplifier output is monitored to determine if the violation is still present. if it is still present, the idle event occurs again, followed by the full chip, power-down sequence. this cycle continues until the violation no longer exists. if the violation disappears, the converter is allowed to switch normally, maintaining regulation. synchronous rectifier the adp1878 / adp1879 employ internal mosfet drivers for the external high- and low-side mosfets. the low-side synchronous rectifier not only improves overall conduction efficiency, but it also ensures proper charging of the bootstrap capacitor located at the high-side driver input. this is beneficial during startup to provide sufficient drive signal to the external high-side mosfet and to attain fast turn-on response, which is essential for minimizing switching losses. the integrated high- and low-side mosfet drivers operate in complementary fashion with built-in anti cross conduction circuitry to prevent unwanted shoot through current that may potentially damage the mosfets or reduce efficiency because of excessive power loss. adp1879 power saving mode (psm) a power saving mode is provided in the adp1879 . the adp1879 operates in the discontinuous conduction mode (dcm) and pulse skips at light to medium load currents. the controller outputs pulses as necessary to maintain output regulation. unlike the continuous conduction mode (ccm), dcm operation prevents negative current, thus allowing improved system efficiency at light loads. current in the reverse direction through this pathway, however, results in power dissipation and, therefore, a decrease in efficiency. figure 74. discontinuous mode of operation (dcm) to minimize the chance of negative inductor current buildup, an on-board zero-cross comparator turns off all high- and low- side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the high- and low-side mosfets are turned off. to ensure idle mode entry, a 10 mv offset, connected in series at the sw node, is implemented (see figure 75). figure 75. zero-cross comparator with 10 mv of offset as soon as the forward current through the low-side mosfet decreases to a level where 10 mv = i q2 r on(q2) the zero-cross comparator (or i rev comparator) emits a signal to turn off the low-side mosfet. from this point, the slope of the inductor current ramping down becomes steeper (see figure 76) as the body diode of the low-side mosfet begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted. hs clim zero current repeated current-limit violation detected a predetermined number of pulses is counted to allow the converter to cool down soft start is reinitialized to monitor if the violation still exists 09441-073 hs hs and ls are off or in idle mode ls 0a i load as the inductor current approaches zero current, the state machine turns off the lower-side mosfet. t on t off 09441-074 10mv zero-cross comparator q2 ls sw i q2 09441-075
adp1878/adp1879 data sheet rev. a | page 22 of 40 figure 76. 10 mv offset to ensure pr evention of negative inductor current the system remains in idle mode until the output voltage drops below regulation. next, a pwm pulse is produced, turning on the high-side mosfet to maintain system regulation. the adp1879 does not have an internal clock; it switches purely as a hysteretic controller, as described in this section. timer operation the adp1878 / adp1879 employ a constant on-time architecture, which provides a variety of benefits, including improved load and line transient response when compared with a constant (fixed) frequency current-mode control loop of comparable loop design. the constant on-time timer, or t on timer, senses the high-side input voltage (v in ) and the output voltage (v out ) using sw waveform information to produce an adjustable one shot pwm pulse. the pulse varies the on-time of the high-side mosfet in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain output regula- tion. the timer generates an on-time (t on ) pulse that is inversely proportional to v in . where k is a constant that is trimmed using an rc timer product for the 300 khz, 600 khz, and 1.0 mhz frequency options. figure 77. constant on-time time the constant on-time (t on ) is not strictly constant because it varies with v in and v out . however, this variation occurs in such a way as to keep the switching frequency virtually independent of v in and v out . the t on timer uses a feedforward technique that, when applied to the constant on-time control loop, makes it a pseudo fixed frequency to a first-order approximation. second-order effects, such as dc losses in the external power mosfets (see the efficiency consideration section), cause some variation in frequency vs. load current and line voltage. these effects are shown in figure 23 to figure 34. the variations in frequency are much reduced compared with the variations generated if the feedforward technique is not used. the feedforward technique establishes the following relationship: 1 where f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz). the t on timer senses v in and v out to minimize frequency variation as previously explained. this provides pseudo fixed frequency as explained in the pseudo fixed frequency section. to a l low he adro om for v in and v out sensing, adhere to the following equations: v reg v in /8 + 1.5 v reg v out /4 for typical applications where v reg is 5 v, these equations are not relevant; however, for lower v reg inputs, care may be required. pseudo fixed frequency the adp1878 / adp1879 employ a constant on-time control scheme. during steady state operation, the switching frequency stays relatively constant, or pseudo fixed. this is due to the one shot t on timer that produces a high-side pwm pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. during load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation quicker than if the frequency were fixed, or if it were to remain unchanged. after the transient event is complete, the frequency returns to a pseudo fixed value. to illustrate this feature more clearly, this section describes one such load transient eventa positive load stepin detail. during load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off time (drvl on time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. when a positive load step occurs, the error amplifier (out of phase with the output, v out ) produces new voltage information at its output (comp). in addition, the current sense amplifier senses new inductor current information during this positive load transient event. the output voltage reaction of the error amplifier is compared with the new inductor current information that sets the start of the next switching cycle. because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information hs and ls in idle mode 10mv = r on i load zero-cross comparator detects 10mv offset and turns off ls sw ls 0a i load t on another t on edge is triggered when v out falls below regulation 09441-076 c r (trimmed) vreg t on v in i sw information 09441-077
data sheet adp1878/adp1879 rev. a | page 23 of 40 is sensed through the counter action upswing of the output (comp) of the error amplifier. the result is a convergence of these two signals (see figure 78), which allows an instantaneous increase in switching frequency during the positive load transient event. in summary, a positive load step causes v out to transient down, which causes comp to transient up and, therefore, shortens the off time. this resulting increase in frequency during a positive load transient helps to quickly bring v out back up in value and within the regulation window. similarly, a negative load step causes the off time to lengthen in response to v out rising. this effectively increases the inductor demagnetizing phase, helping to bring v out within regulation. in this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. because the adp1878 / adp1879 have the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed frequency equivalent . therefore, using a pseudo fixed frequency results in significantly better load transient performance compared to using a fixed frequency. figure 78. load transient response operation power-good monitoring the adp1878 / adp1879 power-good circuitry monitors the output voltage via the fb pin. the pgood pin is an open- drain output that can be pulled up by an external resistor to a voltage rail that does not necessarily have to be vreg. when the internal nmos switch is in high impedance (off state), this means that the pgood pin is logic high and the output voltage via the fb pin is within the specified regulation window. when the internal switch is turned on, pgood is internally pulled low when the output voltage via the fb pin is outside this regulation window. the power-good window is defined with a typical upper speci- fication of +90 mv and a lower specification of ?70 mv below the fb voltage of 600 mv. when an overvoltage event occurs at the output, there is a typical propagation delay of 12 s prior to the deassertion (logic low) of the pgood pin. when the output voltage reenters the regulation window, there is a propagation delay of 12 s prior to pgood reasserting back to a logic high state. when the output is outside the regulation window, the pgood open-drain switch is capable of sinking 1 ma of current and providing 140 mv of drop across this switch. the user is free to tie the external pull-up resistor (r res ) to any voltage rail up to 20 v. the following equation provides the proper external pull-up resistor value: 140 mv 1 ma where: r pgd is the pgood external resistor. v ext is a user chosen voltage rail. figure 79. power good, output voltage monitoring circuit figure 80. power-good timing diagram, t pgd = 12 s (diagram may look disproportionate for illustration purposes) valley trip points load current demand error amp output pwm output f sw > f sw cs amp output 09441-078 530mv 690mv fb 600mv pgood 1ma ? 140mv + v ext r pgd 09441-079 690mv 640mv 600mv 530mv fb hysteresis (50mv) output o v er v olt a ge pgood deassert pgood reassert pgood assertion at power-up pgood deassertion at power-down soft start v ext pgood 0v 0v t pgd t pgd t pgd t pgd 09441-080
adp1878/adp1879 data sheet rev. a | page 24 of 40 applications information feedback resistor divider the required resistor divider network can be determined for a given v out value because the internal band gap reference (v ref ) is fixed at 0.6 v. selecting values for r t and r b determine the minimum output load current of the converter. therefore, for a given value of r b , the r t value can be determined through the following expression: 0.6 v 0.6 v inductor selection the inductor value is inversely proportional to the inductor ripple current. the peak-to-peak ripple current is given by ? 3 where k i is typically 0.33. the equation for the inductor value is given by ? where: v in is the high voltage input. v out is the desired output voltage. f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz). when selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the valley current-limit setting section and figure 81). figure 81. peak inductor current vs. valley current limit for 33%, 40%, and 50% of inductor ripple current table 8. recommended inductors l (h) dcr (m) i sat (a) dimensions (mm) manufacturer model number 0.12 0.33 55 10.2 7 wrth elek. 744303012 0.22 0.33 30 10.2 7 wrth elek. 744303022 0.47 0.8 50 14.2 12.8 wrth elek. 744355147 0.72 1.65 35 10.5 10.2 wrth elek. 744325072 0.9 1.6 32 14 12.8 wrth elek. 744318120 1.2 1.8 25 10.5 10.2 wrth elek. 744325120 1.0 3.8 16 10.2 10.2 wrth elek. 7443552100 1.4 3.2 24 14 12.8 wrth elek. 744318180 2.0 2.6 23 10.2 10.2 wrth elek. 7443551200 0.8 27.5 sumida cep125u-0r8 output ripple voltage (v rr ) the output ripple voltage is the ac component of the dc output voltage during steady state. for a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. (note that an accuracy of 1.0% is possible during steady state conditions only, not during load transients.) v rr = (0.01) v out output capacitor selection the primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. for a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. the speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. this crossover frequency is determined by the output capacitor, the equivalent series resistance (esr) of the capacitor, and the compensation network. to calculate the small signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation: ? 1 8 ? ? where esr is the equivalent series resistance of the output capacitors. to calculate the output load step, use the following equation: 2 ? ? ? where v droop is the amount that v out is allowed to deviate for a given positive load current step ( i load ). 52 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 6 8 10 12 14 16 18 20 22 24 26 28 30 peak inductor current (a) valley current limit (a) ? i = 50% ? i = 40% ? i = 33% 09441-081
data sheet adp1878/adp1879 rev. a | page 25 of 40 ceramic capacitors are known to have low esr. however, there is a trade-off in using the popular x5r capacitor technology because as much as 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see figure 82). although x7r series capacitors can also be used, the available selection is limited to 22 f maximum. figure 82. capacitance vs. dc voltage characteristics for ceramic capacitors electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. however, because the esr of electrolytic capacitors is much higher than that of ceramic capaci- tors, mount several mlccs in parallel with the electrolytic capacitors to reduce the overall series resistance. compensation network due to its current-mode architecture, the adp1878 / adp1879 require type ii compensation. to determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the overall loop gain (h) of the converter at the unity-gain frequency (f sw /10) when h = 1 v/v: 1 vv ? examining each variable at high frequency enables the unity- gain transfer function to be simplified to provide expressions for the r comp and c comp component values. output filter impedance (z filt ) examining the transfer function of the filter at high frequencies simplifies to 1 1 at the crossover frequency (s = 2f cross ). esr is the equivalent series resistance of the output capacitors. error amplifier output impedance (z comp ) assuming c c2 is significantly smaller than c comp , c c2 can be omitted from the output impedance equation of the error amplifier. the transfer function simplifies to and 1 12 where f zero , the zero frequency, is set to be 1/4 th of the crossover frequency for the adp1878 . error amplifier gain (g m ) the error amplifier gain (transconductance) is g m = 500 a/v (s) current-sense loop gain (g cs ) the current-sense loop gain is 1 ? where: a cs (v/v) is programmable for 3 v/v, 6 v/v, 12 v/v, and 24 v/v (see the programming resistor (res) detect circuit and valley current-limit setting sections). r on is the channel impedance of the low-side mosfet. crossover frequency the crossover frequency is the frequency at which the overall loop (system) gain is 0 db (h = 1 v/v). it is recommended for current-mode converters, such as the adp1878 , that the user set the crossover frequency between 1/10 th and 1/15 th of the switching frequency. 1 12 the relationship between c comp and f zero (zero frequency) is as follows: 1 2 the zero frequency is set to 1/4 th of the crossover frequency. combining all of the above parameters results in 1 1 1 1 where esr is the equivalent series resistance of the output capacitors. 1 2 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 5 10 15 20 25 30 capacitance charge (%) dc voltage (v dc ) x7r (50v) x5r (25v) x5r (16v) 10f tdk 25v, x7r, 1210 c3225x7r1e106m 22f murata 25v, x7r, 1210 grm32er71e226ke15l 47f murata 16v, x5r, 1210 grm32er61c476ke15l 09441-082
adp1878/adp1879 data sheet rev. a | page 26 of 40 efficiency consideration an important criteria to consider in constructing a dc-to-dc converter is efficiency. by definition, efficiency is the ratio of the output power to the input power. for high power applications at load currents of up to 20 a, the following are important mosfet parameters that aid in the selection process: ? v gs (th) is the mosfet voltage applied between the gate and the source that starts channel conduction. ? r ds (on) is the on resistance of the mosfet during channel conduction. ? q g is the total gate charge. ? c n1 is the input capacitance of the high-side switch. ? c n2 is the input capacitance of the low-side switch. the following are the losses experienced through the external component during normal switching operation: ? channel conduction loss (both of the mosfets). ? mosfet driver loss. ? mosfet switching loss. ? body diode conduction loss (low-side mosfet). ? inductor loss (copper and core loss). channel conduction loss during normal operation, the bulk of the loss in efficiency is due to the power dissipated through mosfet channel conduction. power loss through the high-side mosfet is directly proportional to the duty cycle (d) for each switching period, and the power loss through the low-side mosfet is directly proportional to 1 ? d for each switching period. the selection of mosfets is governed by the maximum dc load current that the converter is expected to deliver. in particular, the selection of the low-side mosfet is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. therefore, the low-side mosfet is in the on state for most of the switching period. 1 , 2 1 1 2 mosfet driver loss other dissipative elements are the mosfet drivers. the con- tributing factors are the dc current flowing through the driver during operation and the q gate parameter of the external mosfets. p dr(loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ v reg ( f sw c lowerfet v reg + i bias )] where: c upperfet is the input gate capacitance of the high-side mosfet. c lowerfet is the input gate capacitance of the low-side mosfet. i bias is the dc current flowing into the high- and low-side drivers. v dr is the driver bias voltage (that is, the low input voltage ( v reg ) minus the rectifier drop (see figure 83)). v reg is the bias voltage. figure 83. internal rectifier voltage drop vs. switching frequency mosfet switching loss the sw node transitions due to the switching activities of the high- and low-side mosfets. this causes removal and reple- nishing of charge to and from the gate oxide layer of the mosfet, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. the current that enters and exits these charge paths presents additional loss during these transition times. this can be approxi- mately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions: t sw-trans = r gate c total where: c total is the c gd + c gs of the external mosfet. r gate is the gate input resistance of the external mosfet. the ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: -trans 2 or p sw(loss) = f sw r gate c total i load v in 2 body diode conduction loss the adp1878 / adp1879 employ anti cross conduction circuitry that prevents the high- and low-side mosfets from conducting current simultaneously. this overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. however, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the mosfets change states and continuing well into idle mode. 800 720 640 560 480 400 320 240 160 80 300 1000 900 800 700 600 500 400 rectifier voltage drop (mv) switching frequency (khz) +125c +25c ?40c v reg = 2.7v v reg = 3.6v v reg = 5.5v 09441-083
data sheet adp1878/adp1879 rev. a | page 27 of 40 the amount of loss through the body diode of the low-side mosfet during the anti overlap state is given by the following expression: 2 where: t body(loss) is the body conduction time (refer to figure 84 for dead time periods). t sw is the period per switching cycle. v f is the forward drop of the body diode during conduction. (refer to the selected external mosfet data sheet for more information about the v f parameter.) figure 84. body diode conduction time vs. low voltage input (v reg ) inductor loss during normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (dcr). typically, larger sized inductors have smaller dcr values. the inductor core loss is a result of the eddy currents generated within the core material. these eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. the amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. it is recommended to use shielded ferrite core material type inductors with the adp1878 / adp1879 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (emi). input capacitor selection the goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. the problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (esr) and large equivalent series inductance (esl). aluminum electrolytic capacitors have such high esr that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. if bulk electrolytic capacitors are used, it is recommended to use multilayered ceramic capacitors (mlcc) in parallel due to their low esr values. this dramatically reduces the input voltage ripple amplitude as long as the mlccs are mounted directly across the drain of the high-side mosfet and the source terminal of the low-side mosfet (see the layout considerations section). improper placement and mounting of these mlccs may cancel their effectiveness due to stray inductance and an increase in trace impedance. , , the maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 ? d while the high-side mosfet is in the off state. the input capacitor rms current reaches its maximum at time d. when calculating the maximum input voltage ripple, account for the esr of the input capacitor as follows: v max,ripple = v ripp + ( i load,max esr ) where: v ripp is usually 1% of the minimum voltage input. i load,max is the maximum load current. esr is the equivalent series resistance rating of the input capacitor. inserting v max,ripple into the charge balance equation to calculate the minimum input capacitor requirement gives , , , 1 or , , 4 , where d = 50%. thermal considerations the adp1878 / adp1879 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board ldo, and on-board mosfet drivers. because applications may require up to 20 a of load current and be subjected to high ambient temperature, the selection of external high- and low-side mosfets must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125c. to avoid permanent or irreparable damage, if the junction temper- ature reaches or exceeds 155c, the part enters thermal shutdown, turning off both external mosfets, and is not reenabled until the junction temperature cools to 140c (see the on-board low dropout (ldo) regulator section). in addition, it is important to consider the thermal impedance of the package. because the adp1878 / adp1879 employ an on-board ldo, the ac current (fxcxv) consumed by the internal drivers to drive the external mosfets, adds another element of 80 72 64 56 48 40 32 24 16 8 2.7 5.5 4.8 4.1 3.4 body diode conduction time (ns) v reg (v) +125c +25c ?40c 1mhz 300khz 09441-084
adp1878/adp1879 data sheet rev. a | page 28 of 40 power dissipation across the internal ldo. equation 3 shows the power dissipation calculations for the integrated drivers and for the internal ldo. table 9 lists the thermal impedance for the adp1878 / adp1879 , which are available in a 14-lead lfcsp_wd. table 9. thermal impedance for 14-lead lfcsp_wd package thermal impedance 14-lead lfcsp_wd ja 4-layer board 30c/w figure 85 specifies the maximum allowable ambient temperature that can surround the adp1878 / adp1879 ic for a specified high input voltage (v in ). figure 85 illustrates the temperature derating conditions for each available switching frequency for low, typical, and high output setpoints for the 14-lead lfcsp_wd package. all temperature derating criteria are based on a maximum ic junction temperature of 125c. figure 85. ambient temperature vs. v in , 4-layer evaluation board, c in = 4.3 nf (high-/low-side mosfet) the maximum junction temperature allowed for the adp1878 / adp1879 ic is 125c. this means that the sum of the ambient temperature (t a ) and the rise in package temperature (t r ), which is caused by the thermal impedance of the package and the internal power dissipation, should not ex ceed 125c, as dictated by the following expression: t j = t r t a (1) where: t j is the maximum junction temperature. t r is the rise in package temperature due to the power dissipated from within. t a is the ambient temperature. the rise in package temperature is directly proportional to its thermal impedance characteristics. the following equation represents this proportionality relationship: t r = ja p dr(loss) (2) where: ja is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. p dr(loss) is the overall power dissipated by the ic. the bulk of the power dissipated is due to the gate capacitance of the external mosfets and current running through the on-board ldo. the power loss equations for the mosfet drivers and internal low dropout regulator (see the mosfet driver loss section and the efficiency consideration section) are: p dr(loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ v reg ( f sw c lowerfet v reg + i bias )] (3) where: c upperfet is the input gate capacitance of the high-side mosfet. c lowerfet is the input gate capacitance of the low-side mosfet. i bias is the dc current (2 ma) flowing into the high- and low- side drivers. v dr is the driver bias voltage (the low input voltage (v reg ) minus the rectifier drop (see figure 83)). v reg is the ldo output/bias voltage. p diss(ldo) = p dr(loss) + ( v in C v reg ) (f sw c total v reg + i bias (4) where p diss(ldo) is the power dissipated through the pass device in the ldo block across v in and v reg . p dr(loss) is the mosfet driver loss. v in is the high voltage input. v reg is the ldo output voltage and bias voltage. c total is the c gd + c gs of the external mosfet. i bias is the dc input bias current. for example, if the external mosfet characteristics are ja (14-lead lfcsp_wd) = 30c/w, f sw = 300 khz, i bias = 2 ma, c upperfet = 3.3 nf, c lowerfet = 3.3 nf, v dr = 4.62 v, and v reg = 5.0 v, then the power loss is p dr(loss) = [ v dr ( f swcupperfet v dr + i bias )] + [ v reg ( f swclowerfet v reg + i bias )] = (4.62 (300 10 3 3.3 10 ?9 4.62 + 0.002)) + (5.0 (300 10 3 3.3 10 ?9 5.0 + 0.002)) = 57.12 mw p diss(ldo) = ( v in C v reg ) (f sw c total v reg + i bias ) = (13 v C 5 v) (300 10 3 3.3 10 ?9 5 + 0.002) = 55.6 mw p diss(total) = p diss(ldo) + p dr(loss) = 77.13 mw + 55.6 mw = 132.73 mw 130 90 100 110 120 5.5 19.0 17.5 16.0 14.5 13.0 11.5 10.0 8.5 7.0 maximum allowable ambient temperature (c) v in (v) 09441-085 300khz 600khz 1mhz v out = 0.8v v out = 1.8v v out = high setpoint
data sheet adp1878/adp1879 rev. a | page 29 of 40 the rise in package temperature (for a 14-lead lfcsp_wd) is t r = ja p dr(loss) = 30c 132.05 mw = 4.0c assuming a maximum ambient temperature environment of 85c, t j = t r t a = 4.0c + 85c = 89.0c, which is below the maximum junction temperature of 125c. design example the adp1878 / adp1879 are easy to use, requiring only a few design criteria. for example, the example outlined in this section uses only four design criteria: v out = 1.8 v, i load = 15 a (pulsing), v in = 12 v (typical), and f sw = 300 khz. input capacitor the maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 v 0.01 = 120 mv). v ripp = 120 mv v max,ripple = v ripp ? ( i load,max esr ) = 120 mv ? (15 a 0.001) = 45 mv , , 4 , 15 a 4 300 10 105 mv = 120 f choose five 22 f ceramic capacitors. the overall esr of five 22 f ceramic capacitors is less than 1 m. i rms = i load /2 = 7.5 a p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw inductor determining inductor ripple current amplitude: ? 3 5 a then, calculating for the inductor value , ? , 13.2 v C 1.8 v 5 v 300 10 1.8 v 13.2 v = 1.03 h the inductor peak current is approximately 15 a + (5 a 0.5) = 17.5 a therefore, an appropriate inductor selection is 1.0 h with dcr = 3.3 m (wrth elektronik 7443552100) with a peak current handling of 20 a. = 0.003 (15 a) 2 = 675 mw current-limit programming the valley current is approximately 15 a ? (5 a 0.5) = 12.5 a assuming a low-side mosfet r on of 4.5 m and 13 a, as the valley current limit from table 7 and figure 71 indicate, a pro- gramming resistor (res) of 100 k corresponds to an a cs of 24 v/v. choose a programmable resistor of r res = 100 k for a current sense gain of 24 v/v. output capacitor assume that a load step of 15 a occurs at the output and no more than 5% output deviation is allowed from the steady state operating point. in this case, the advantage of the adp1878 is that because the frequency is pseudo fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. v droop = 0.05 1.8 v = 90 mv assuming the overall esr of the output capacitor ranges from 5 m to 10 m, 2 ? ? 2 15 a 300 10 90 mv = 1.11 mf therefore, an appropriate inductor selection is five 270 f polymer capacitors with a combined esr of 3.5 m. assuming an overshoot of 45 mv, determine if the output capacitor that was calculated previously is adequate ? 110 15 a 1.8 45 mv 1.8 = 1.4 mf choose five 270 f polymer capacitors. the rms current through the output capacitor is 1 2 1 3 , , 1 2 1 3 13.2 v C 1.8 v 1 f30010 3 1.8 v 13.2 v 1.49 a the power loss dissipated through the esr of the output capacitor is p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw
adp1878/adp1879 data sheet rev. a | page 30 of 40 feedback resistor network setup choosing r b = 1 k as an example. calculate r t as follows: 1 k 1.8 v 0.6 v 0.6 v 2 k compensation network to ca lc u late r comp , c comp , and c par , the transconductance parameter and the current sense gain variable are required. the transconductance parameter (g m ) is 500 a/v, and the current sense loop gain is 1 1 24 0.005 8.33 a/v where a cs and r on are taken from setting up the current limit (see the programming resistor (res) detect circuit section and the valley current-limit setting section). the crossover frequency is 1/12 th of the switching frequency: 300 khz/12 = 25 khz the zero frequency is 1/4 th of the crossover frequency: 25 khz/4 = 6.25 khz 1 1 1 1 25 k 25 k 6.25 k 1 2 25 k 1.8/15 0.0035 0.0011 1 2 25 k 0.0035 0.0011 1.8 0.6 1 500 10 8.3 15 1.8 = 60.25 k 1 2 1 2 3.14 60.25 10 6.2510 = 423 pf loss calculations duty cycle = 1.8/12 v = 0.15 r on(n2) = 5.4 m t body(loss) = 20 ns (body conduction time) v f = 0.84 v (mosfet forward voltage) c in = 3.3 nf (mosfet gate input capacitance) q n1,n2 = 17 nc (total mosfet gate charge) r gate = 1.5 (mosfet gate input resistance) 1 , 1 1 = (0.15 0.0054 + 0.85 0.0054) (15 a) 2 = 1.215 w 2 = 20 ns 300 10 3 15 a 0.84 2 = 151.2 mw p sw(loss) = f sw r gate c total i load v in 2 = 300 10 3 1.5 3.3 10 ?9 15 a 12 2 = 534.6 mw p dr(loss) = [v dr (f sw c upperfet v dr + i bias )] + [ v reg ( f sw c lowerfet v reg + i bias )] =(4.62 (300 10 3 3.3 10 ?9 4.62 + 0.002)) + (5.0 (300 10 3 3.3 10 ?9 5.0 + 0.002)) = 57.12 mw p diss(ldo) = ( v in C v reg ) (f sw c total v reg + i bias ) = (13 v C 5 v) (300 10 3 3.3 10 ?9 5 + 0.002) = 55.6 mw p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw 2 )( load lossdcr idcr p ?? = 0.003 (15 a) 2 = 675 mw p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw p loss = p n1,n2 + p body(loss) + p sw + p dcr + p dr + p diss(ldo) + p cout + p cin = 1.215 w + 151.2 mw + 534.6 mw + 57.12 mw + 55.6 + 3.15 mw + 675 mw + 56.25 mw = 2.655 w
data sheet adp1878/adp1879 rev. a | page 31 of 40 external component recommendations the configurations listed in table 10 are with f cross = 1/12 f sw , f zero = ? f cross , r res = 100 k, r bot = 1k, r on = 5.4 m (bsc042n03ms g), vreg = 5 v (float), and a maximum load current of 14 a. the adp1879 models listed in table 10 are the psm versions of the device. table 10. external component values model v out (v) v in (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) adp1878acpz-0.3-r7/ 0.8 13 5 22 2 5 560 3 0.72 56.9 620 62 0.3 adp1879acpz-0.3-r7 1.2 13 5 22 2 4 560 3 1.0 56.9 620 62 1.0 1.8 13 4 22 2 4 270 4 1.2 56.9 470 47 2.0 2.5 13 4 22 2 3 270 4 1.53 57.6 470 47 3.2 3.3 13 5 22 2 2 330 5 2.0 56.9 470 47 4.5 5 13 4 22 2 330 5 3.27 40.7 680 68 7.3 7 13 4 22 2 22 2 + ( 4 47 6 ) 3.44 40.7 680 68 10.7 1.2 16.5 4 22 2 4 560 3 1.0 56.9 620 62 1.0 1.8 16.5 3 22 2 4 270 4 1.0 56.9 470 47 2.0 2.5 16.5 3 22 2 4 270 4 1.67 57.6 470 47 3.2 3.3 16.5 3 22 2 2 330 5 2.00 56.9 510 51 4.5 5 16.5 3 22 2 2 150 7 3.84 41.2 680 68 7.3 7 16.5 3 22 2 22 2 + 4 47 6 4.44 40.7 680 68 10.7 adp1878acpz-0.6-r7/ 0.8 5.5 5 22 2 4 560 3 0.22 56.2 300 300 0.3 adp1879acpz-0.6-r7 1.2 5.5 5 22 2 4 270 4 0.47 56.9 270 27 1.0 1.8 5.5 5 22 2 3 270 4 0.47 56.9 220 22 2.0 2.5 5.5 5 22 2 3 180 8 0.47 56.9 220 22 3.2 1.2 13 3 22 2 5 270 4 0.47 56.9 360 36 1.0 1.8 13 5 10 9 3 330 5 0.47 56.2 270 27 2.0 2.5 13 5 10 9 3 270 4 0.90 57.6 240 24 3.2 3.3 13 5 10 9 2 270 4 1.00 57.6 240 24 4.5 5 13 5 10 9 150 7 1.76 40.7 360 36 7.3 1.2 16.5 3 10 9 4 270 4 0.47 56.9 300 30 1.0 1.8 16.5 4 10 9 2 330 5 0.72 53.6 270 27 2.0 2.5 16.5 4 10 9 3 270 4 0.90 57.6 270 27 3.2 3.3 16.5 4 10 9 330 5 1.0 53.0 270 27 4.5 5 16.5 4 10 9 4 47 6 2.0 41.2 360 36 7.3 7 16.5 4 10 9 3 47 6 2.0 40.7 300 30 10.7 adp1878acpz-1.0-r7/ 0.8 5.5 5 22 2 4 270 4 0.22 54.9 200 20 0.3 adp1879acpz-1.0-r7 1.2 5.5 5 22 2 2 330 5 0.22 49.3 220 22 1.0 1.8 5.5 3 22 2 3 180 8 0.22 56.9 130 13 2.0 2.5 5.5 3 22 2 270 4 0.22 54.9 130 13 3.2 1.2 13 3 10 9 3 330 5 0.22 53.6 200 20 1.0 1.8 13 4 10 9 3 270 4 0.47 56.9 180 18 2.0 2.5 13 4 10 9 270 4 0.47 54.9 180 18 3.2 3.3 13 5 10 9 270 4 0.72 56.2 180 18 4.5 5 13 4 10 9 3 47 6 1.0 40.7 220 22 7.3 1.2 16.5 3 10 9 4 270 4 0.47 56.9 270 27 1.0 1.8 16.5 3 10 9 3 270 4 0.47 56.9 220 22 2.0 2.5 16.5 4 10 9 3 180 8 0.72 56.9 200 20 3.2 3.3 16.5 4 10 9 270 4 0.72 56.2 180 18 4.5 5 16.5 3 10 9 3 47 6 1.2 40.7 220 22 7.3 7 16.5 3 10 9 22 2 + 47 6 1.2 40.7 180 18 10.7 1 see the inductor selection section and table 11. 2 22 f murata 25 v, x7r, 1210 grm32er 71e226ke15l (3.2 mm 2.5 mm 2.5 mm). 3 560 f panasonic (sp-series ) 2 v, 7 m, 3.7 a eefue0d561lr (4.3 mm 7.3 mm 4.2 mm). 4 270 f panasonic (sp-series) 4 v, 7 m, 3.7 a eefue0g271lr (4.3 mm 7.3 mm 4.2 mm). 5 330 f panasonic (sp-series) 4 v, 12 m, 3.3 a eefue0g331r (4.3 mm 7.3 mm 4.2 mm). 6 47 f murata 16 v, x5r, 1210 grm32er 61c476ke15l (3.2 mm 2.5 mm 2.5 mm). 7 150 f panasonic (sp-series) 6.3 v, 10 m , 3.5 a eefue0j151xr (4.3 mm 7.3 mm 4.2 mm). 8 180 f panasonic (sp-series) 4 v, 10 m, 3.5 a eefue0g181xr (4.3 mm 7.3 mm 4.2 mm). 9 10 f tdk 25 v, x7r, 1210 c3225x7r1e106m.
adp1878/adp1879 data sheet rev. a | page 32 of 40 table 11. recommended inductors l (h) dcr (m) i sat (a) dimension (mm) manufacturer model number 0.12 0.33 55 10.2 7 wrth elektronik 744303012 0.22 0.33 30 10.2 7 wrth elektronik 744303022 0.47 0.8 50 14.2 12.8 wrth elektronik 744355147 0.72 1.65 35 10.5 10.2 wrth elektronik 744325072 0.9 1.6 32 14 12.8 wrth elektronik 744318120 1.2 1.8 25 10.5 10.2 wrth elektronik 744325120 1.0 3.8 16 10.2 10.2 wrth elektronik 7443552100 1.4 3.2 24 14 12.8 wrth elektronik 744318180 2.0 2.6 23 10.2 10.2 wrth elektronik 7443551200 0.8 27.5 sumida cep125u-0r8 table 12. recommended mosfets v gs = 4.5 v r on (m) i d (a) v ds (v) c in (nf) q total (nc) package manufacturer model number high-side mosfet (q1/q2) 5.4 47 30 3.2 20 pg-tdson8 infineon bsc042n03ms g 10.2 53 30 1.6 10 pg-tdson8 infineon bsc080n03ms g 6.0 19 30 35 so-8 vishay si4842dy 9 14 30 2.4 25 so-8 international rectifier irf7811 low-side mosfet (q3/q4) 5.4 47 30 3.2 20 pg-tdson8 infineon bsc042n03ms g 10.2 82 30 1.6 10 pg-tdson8 infineon bsc080n03ms g 6.0 19 30 35 so-8 vishay si4842dy
data sheet adp1878/adp1879 rev. a | page 33 of 40 layout considerations the performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (pcb). optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulation specifications, and reduce pwm jitter and electromagnetic interference. figure 86 shows the schematic of a typical adp1878 / adp1879 used for a high current application. blue traces denote high current pathways. vin, pgnd, and v out traces should be wide and possibly replicated, descending down into the multiple layers. vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of q1/q2, the drain of q3/q4, and the inductor. figure 86. adp1878 high current evaluation board schematic (blue traces indicate high current paths) figure 87. overall layout of the adp1878/adp1879 high current evaluation board murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m ? , eefue0g271lr infineon fets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1h, 3.8m ? , 16a, 7443552100 q3 q4 q1 q2 high voltage input v in = 12v c bst 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.0h r snb 2 ? c snb 1.5nf r top 2k? r7 10k ? r bot 1k? v out 1 vin 14 bst 2 comp 13 sw 3 en 12 drvh 5 gnd 10 drvl adp1878/ adp1879 c c 430pf c par 53pf r c 57k ? c1 1f c vin 22f c2 0.1f jp3 r res 100k ? 4 fb 11 pgnd 6 res 9 pgood 7 vreg 8 ss 5k? v reg c ss 34nf v reg 09441-086 input capacitors are mounted close to drain of q1/q2 and source of q3/q4 separate analog ground plane for compensation and feedback resistors sensitive analog components located far from noisy power section output capacitors are mounted at rightmost area of evaluation board 0 9441-087
adp1878/adp1879 data sheet rev. a | page 34 of 40 figure 88. layer 2 of evaluation board figure 89. layer 3 of evaluation board 09441-088 top resistor feedback tap vout sense tap line extending back to the top resistor in the feedback divider network. this overlaps with pgnd sense tap line extending to the analog ground plane 09441-089
data sheet adp1878/adp1879 rev. a | page 35 of 40 figure 90. layer 4 (bottom layer) of evaluation board ic section (left side of evaluation board) a dedicated plane for the analog ground plane (gnd) should be separate from the main power ground plane (pgnd). with the shortest path possible, connect the analog ground plane to the gnd pin (pin 5). place this plane on the top layer only of the evaluation board. to avoid crosstalk interference, do not allow any other voltage or current pathway directly below this plane on layer 2, layer 3, or layer 4. connect the negative terminals of all sensitive analog components to the analog ground plane. examples of such sensitive analog components include the bottom resistor of the resistor divider, the high frequency bypass capacitor for biasing (0.1 f), and the compensation network. mount a 1 f bypass capacitor directly across the vreg pin (pin 7) and the pgnd pin (pin 11). in addition, tie a 0.1 f across the vreg pin (pin 7) and the gnd pin (pin 5). power section as shown in figure 87, an appropriate configuration to localize large current transfer from the high voltage input (v in ) to the output (v out ) and then back to the power ground is to put the v in plane on the left, the output plane on the right, and the main power ground plane in between the two. current transfers from the input capacitors to the output capacitors, through q1/q2, during the on state (see figure 91). the direction of this current (yellow arrow) is maintained as q1/q2 turns off and q3/q4 turns on. when q3/q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the power ground terminal of the bulk capacitor to the output capacitors, through the q3/q4. arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through q1/q2 stops abruptly. sudden changes in flux, usually at the source terminals of q1/q2 and the drain terminal of q3/q4, cause large dv/dt at the sw node. the sw node is near the top of the evaluation board. the sw node should use the least amount of area possible and be away from any sensitive analog circuitry and components. this is because the sw node is where most sudden changes in flux density occur. when possible, replicate this pad onto layer 2 and layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the sw node plane. populate the sw node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of q1/q2 and the drain of q3/q4. the output voltage power plane (v out ) is at the rightmost end of the evaluation board. this plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. ensure that the negative terminals of the output capacitors are placed close to the main power ground (pgnd), as previously mentioned. all of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between d and 1 ? d. bottom resistor tap to analog ground plane pgnd sense tap from negative terminals of the output bulk capacitors. this track placement should be directly below the vout sense line of layer 3. 09441-090
adp1878/adp1879 data sheet rev. a | page 36 of 40 figure 91. primary current pathways during the on state of the high-side mosfet (left arrow) and the on state of the low-side mosfet (right arrow) differential sensing because the adp1878 / adp1879 operate in valley current-mode control, a differential voltage reading is taken across the drain and source of the low-side mosfet. connect the drain of the low-side mosfet s as close as possible to the sw pin (pin 13) of the ic. likewise, connect the source as close as possible to the pgnd pin (pin 11) of the ic. when possible, keep both of these track lines narrow and away from any other active device or voltage/current path. figure 92. drain/source tracking tapp ing of the low-side mosfet for cs amp differential sensing (yellow sense line on layer 2) in addition, employ differential sensing between the outermost output capacitor and the feedback resistor divider (see figure 89 and figure 90). connect the positive terminal of the output capacitor to the top resistor (r t ). connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. keep both of these track lines, as previously mentioned, narrow and away from any other active device or voltage/ current path. 09441-091 layer 1: sense line for sw (drain of lower mosfet) layer 1: sense line for pgnd (source of lower mosfet) pgnd sw 09441-092
data sheet adp1878/adp1879 rev. a | page 37 of 40 typical application circuits 12 a, 300 khz high current application circuit figure 93. application circuit for 12 v input, 1.8 v output, 12 a, 300 khz (q2/q4 no connect) 5.5 v input, 600 khz current application circuit figure 94. application circuit for 5.5 v input, 2.5 v output, 12 a, 600 khz (q2/q4 no connect) murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f (sp-series), 4v, 7m ? , eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1.2h, 2m ? , 20a, 744325120 q3 q4 q1 q2 high voltage input v in = 12v c bst 100nf v out = 1.8v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.2h r snb 2 ? c snb 1.5nf r top 2k? r7 10k ? r bot 1k? v out 1 vin 14 bst 2 comp 13 sw 3 en 12 drvh 5 gnd 10 drvl adp1878/ adp1879 c c 560pf c par 56pf r c 49.3k ? c1 1f c vin 22f c2 0.1f jp3 r res 100k ? 4 fb 11 pgnd 6 res 9 pgood 7 vreg 8 ss 5k? v reg c ss 34nf v reg 09441-093 murata: (input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 180f (sp-series), 4v, 10m ? , eefue0g181xr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 0.47h, 0.8m ? , 30a, 744355147 q3 q4 q1 q2 high voltage input v in = 5.5v c bst 100nf v out = 2.5v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 n/a + c22 180f + c21 180f + c20 180f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 0.47h r snb 2 ? c snb 1.5nf r top 32k ? r7 10k ? r bot 1k? v out 1 vin 14 bst 2 comp 13 sw 3 en 12 drvh 5 gnd 10 drvl adp1878/ adp1879 c c 220pf c f 22pf r c 56.9k ? c1 1f c vin 22f c2 0.1f jp3 r res 100k ? 4 fb 11 pgnd 6 res 9 pgood 7 vreg 8 ss 5k? v reg c ss 34nf v reg 09441-094
adp1878/adp1879 data sheet rev. a | page 38 of 40 300 khz high current application circuit figure 95. application circuit for 13 v input, 1.8 v output, 12 a, 300 khz (q2/q4 no connect) murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f (sp-series), 4v, 7m ? , eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1.2h, 2m ? , 20a, 744325120 q3 q4 q1 q2 high voltage input v in = 13v c bst 100nf v out = 1.8v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.2h r snb 2 ? c snb 1.5nf r top 2k? r7 10k ? r bot 1k? v out 1 vin 14 bst 2 comp 13 sw 3 en 12 drvh 5 gnd 10 drvl adp1878/ adp1879 c c 560pf c par 56pf r c 49.3k ? c1 1f c vin 22f c2 0.1f jp3 r res 100k ? 4 fb 11 pgnd 6 res 9 pgood 7 vreg 8 ss 5k? v reg c ss 34nf v reg 09441-095
data sheet adp1878/adp1879 rev. a | page 39 of 40 packaging and ordering information outline dimensions figure 96. 14-lead lead frame chip scale package [lfcsp_wd] 4 mm 3 mm body, very very thin dual (cp-14-2) dimensions shown in millimeters 101309-a compliant to jedec standards mo-229-wegd bottom view top view end view side view 1 7 8 14 seating plane 0.80 0.75 0.70 0.30 0.25 0.20 0.05 max 0.02 nom 0.15 ref 0.10 ref 0.90 ref 0.30 ref 0.50 bsc coplanarity 0.08 pin 1 indicator (laser marking) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed pad 0.50 0.40 0.30 1.80 1.70 1.55 3.40 3.30 3.15 3.10 3.00 2.90 4.10 4.00 3.90 0.20 min
adp1878/adp1879 data sheet rev. a | page 40 of 40 ordering guide model 1 temperature range package description package option adp1878acpz-0.3-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1878acpz-0.6-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1878acpz-1.0-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1878-0.3-evalz evaluation board adp1878-0.6-evalz evaluation board adp1878-1.0-evalz evaluation board adp1879acpz-0.3-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1879acpz-0.6-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1879acpz-1.0-r7 ?40c to +125c 14-lead frame chip scale package [lfcsp_wd] cp-14-2 adp1879-0.3-evalz evaluation board adp1879-0.6-evalz evaluation board adp1879-1.0-evalz evaluation board 1 z = rohs compliant part. ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09441-0-6/12(a) www.analog.com/adp1878/adp1879

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